As Silicon Wafers Get Thinner, Crack Risk Climbs — How Much and How Often Should O&M-Stage EL Sampling Be?

ⓘ This article is currently published in Chinese. An English version is being prepared — read the Chinese original.

N-type modules (TOPCon, HJT, BC) have pushed wafer thickness down from the roughly 180 microns of the PERC era toward 130 microns and, on some lines, 110 microns. Thinner wafers mean higher power per gram of silicon, but also lower mechanical strength and a greater tendency to develop micro-cracks during transport, installation and years of wind and thermal cycling in the field. For an operating plant with hundreds of thousands of modules, full EL inspection of every panel is neither affordable nor practical, so field EL is almost always a sampling exercise — and a badly designed sample can miss exactly the clustered cracks that matter. This article treats O&M-stage EL sampling as an engineering design problem rather than a formality: why thin-wafer modules change the risk picture, why simple random sampling under-catches clustered defects, how to stratify the sample by incoming batch, transport route, install crew, terrain and string position, how to set the sampling ratio and re-inspection interval around the grid-connection first-year stress-release window and the plant's real degradation and weather exposure, and how to grade what you find against IEC 62446-1 and IEC 61215 defect classes instead of an arbitrary in-house rule. It also explains the practical two-tier workflow most plants converge on — wide-area daytime UAV EL screening to find suspect strings, then portable EL re-inspection of those strings — and where AI-assisted reading raises sampling throughput so the plan is actually executable at plant scale.